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general description the max5941a/max5941b integrate a complete power ic for powered devices (pd) in a power-over-ethernet (poe) system. the max5941a/max5941b provide a pd interface and a compact dc-dc pwm controller suitable for flyback and forward converters in either isolated or nonisolated designs. the max5941a/max5941b pd interface complies with the ieee 802.3af standard, providing the pd with a detec- tion signature, a classification signature, and an integrat- ed isolation switch with programmable inrush current control. these devices also feature power-mode under- voltage lockout (uvlo) with wide hysteresis and power- good status outputs. the max5941a/max5941b also integrate all the building blocks necessary for implementing dc-dc fixed- frequency isolated power supplies. these devices are a current-mode controller with an integrated high startup circuit suitable for isolated telecom/industrial voltage- range power supplies. a high-voltage startup circuit allows the pwm controller to draw power directly from the 18v to 67v input supply during startup. the switching fre- quency is internally trimmed to 275khz ?0%, thus reducing magnetics and filter components. the max5941a allows an 85% operating duty cycle and can be used to implement flyback converters. the max5941b limits the operating duty cycle to less than 50% and can be used in single-ended forward converters. the max5941a/max5941b are designed to work with or with- out an external diode bridge in front of the pd. the max5941a/max5941b are available in 16-pin so packages. applications ip phones wireless access nodes internet appliances computer telephony security cameras power devices in power-over-ethernet/ power-over-mdi features powered device interface fully integrated ieee 802.3af-compliant pd interface pd detection and programmable classification signatures less than 10a leakage current offset during detection integrated mosfet for isolation and inrush current limiting gate output allows external control of the internal isolation fet programmable inrush current control programmable undervoltage lockout pwm controller wide input range: 18v to 67v current-mode control leading-edge blanking internally trimmed 275khz 10% oscillator soft-start max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices ________________________________________________________________ maxim integrated products 1 ordering information 19-3069; rev 0; 10/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package m a x d u t y c yc l e ( % ) max5941aese -40? to +85? 16 so 85 max5941acse 0? to +70? 16 so 85 max5941bese -40? to +85? 16 so 50 max5941bcse 0? to +70? 16 so 50 typical operating circuit appears at end of data sheet. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v+ v cc ndrv v- cs gnd pgood pgood out top view max5941a max5941b so v dd opto rcl ss_shdn ulvo gate v ee pin configuration
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = open, v- tied to out, v+ tied to gnd, uvlo = v ee , t a = t min to +t max , unless otherwise noted. typical values are at t a = +25 c. all voltages are referenced to v ee , unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages are referenced to v ee , unless otherwise noted.) gnd........................................................................-0.3v to +80v out, pgood ...........................................-0.3v to (gnd + 0.3v) rcl, gate .............................................................-0.3v to +12v uvlo ........................................................................-0.3v to +8v pgood to out.........................................-0.3v to (gnd + 0.3v) v+ to v-...................................................................-0.3v to +80v v dd to v-.................................................................-0.3v to +40v v cc to v-..............................................................-0.3v to +12.5v opto, ndrv, ss_ shdn , cs to v-.............-0.3v to (v cc + 0.3v) maximum input/output current (continuous) out to v ee ...................................................................500ma gnd, rcl to v ee ............................................................70ma uvlo, pgood , pgood to v ee .....................................20ma gate to v ee ....................................................................80ma v dd , v cc .........................................................................20ma ndrv continuous ...........................................................25ma ndrv (pulsed for less than 1?) .......................................?a continuous power dissipation (t a = +70?) 16-pin so (derate 9.1mw/? above +70?)................727mw operating temperature range max5941_cse ..................................................0? to +70? max5941_ese ...............................................-40? to +85? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units pd interface detection mode input offset current i offset v i n = 1.4v to 10.1v , g n d = v - = ou t = v + (note 2) 10 a effective differential input resistance dr v i n = 1.4v up to 10.1v w i th 1v step , ou t = p go od = gn d = o u t = v + ( n ote 3) 550 k ? classification mode classification current turn-off threshold v th , clss v in rising (note 4) 20.8 21.8 22.5 v class 0, r cl = 10k ? 02 class 1, r cl = 732 ? 9.17 11.83 class 2, r cl = 392 ? 17.29 19.71 class 3, r cl = 255 ? 26.45 29.55 classification current (notes 5, 6) i class v in = 12.6v to 20v, r disc = 25.5k ? class 4, r cl = 178 ? 36.6 41.4 ma power mode operating supply voltage v in v in = (gnd - v ee )67v operating supply current i in measure at gnd, not including r disc 0.4 1 ma default power turn-on voltage v uvlo , on v in increasing, uvlo = v ee 37.4 38.6 40.1 v default power turn-off voltage v uvlo , off v in decreasing, uvlo = v ee 30 v default power turn-on/off hysteresis v hyst, uvlo 7.4 v external uvlo programming range v in,ex set uvlo externally (note 7) 12 67 v uvlo external reference voltage v ref , uvlo v uvlo increasing 2.400 2.460 2.522 v
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units uvlo external reference voltage hysteresis hyst ratio to v ref,uvlo 19.2 20 20.9 % uvlo bias current i uvlo uvlo = 2.460v -1.5 +1.5 a uvlo input ground sense threshold v th , g , uvlo (note 8) 50 440 mv uvlo input ground sense glitch rejection uvlo = v ee 7s power turn-off voltage, undervoltage lockout deglitch time t off_dly v in , v uvlo falling (note 9) 0.32 ms t a = +25 c (note 11) 0.6 1.1 isolation switch n-channel mosfet on-resistance r on output current = 300ma, v gate = 5.6v, measured between out and v ee t a = +85 c 0.8 1.5 ? isolation switch n-channel mosfet off-threshold voltage v gsth out = gnd, v gate - v ee , output current < 1a 0.5 v gate pulldown switch resistance r g power-off mode, v in = 12v, uvlo = v ee 38 80 ? gate charging current i g v gate = 2v 5 10 15 a gate high voltage v gate i gate = 1a 5.58 5.76 5.93 v v out - v ee , |v out - v ee | decreasing, v gate = 5.75v 1.15 1.23 1.31 v pgood, pgood assertion v out threshold v outen hysteresis 70 mv (gate - v ee ) increasing, out = v ee 4.62 4.76 4.91 v pgood, pgood assertion v gate threshold v gsen hysteresis 80 mv pgood output low voltage i sink = 2ma (note 10) 0.4 v pgood output low voltage v oldcdc i sink = 2ma, out (gnd - 5v) (note 10) 0.2 v pgood leakage current g ate = hi g h, gn d - v ou t = 67v ( n ote 10) 1 a pgood leakage current gate = v e e , pgo od - v e e = 67v ( n ote 10) 1 a electrical characteristics (continued) (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = open, v- tied to out, v+ tied to gnd, uvlo = v ee , t a = t min to +t max , unless otherwise noted. typical values are at t a = +25 c. all voltages are referenced to v ee , unless otherwise noted.) (note 1) electrical characteristics (pwm controller) (all voltages referenced to v-. v dd = 13v, a 10f capacitor connects v cc to v-, v cs = v-, v+ = 48v, 0.1f capacitor connected to ss_ shdn , ndrv = open circuit, opto = v-, t a = t min to +t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units supply current i v+(ns) v dd = 0v, v+ = 67v, driver not switching 0.85 1.3 v+ supply current i v+(s) v+ = 67v, v dd = 0v, v opto = 4v, driver switching 1.4 2.6 ma v+ supply current after startup v+ = 67v, v dd = 13v, v opto = 4v 11 a i vdd ( ns ) v dd = 36v, driver not switching 0.9 1.3 v dd supply current i vdd(s) v dd = 36v, driver switching, v opto = 4v 1.9 2.7 ma
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 4 _______________________________________________________________________________________ electrical characteristics (pwm controller) (continued) (all voltages referenced to v-. v dd = 13v, a 10f capacitor connects v cc to v-, v cs = v-, v+ = 48v, 0.1f capacitor connected to ss_ shdn , ndrv = open circuit, opto = v-, t a = t min to +t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units v+ shutdown current v ss_ shdn = 0v, v+ = 67v 190 290 a v dd shutdown current v ss_ shdn = 0v 8 20 a preregulators/startup v+ input voltage 18 67 v v dd supply voltage 13 36 v internal regulators powered from v+, i cc = 7.5ma, v dd = 0v 7.5 9.8 12 v cc output voltage powered from v dd , i cc = 7.5ma 9.0 10.0 11.0 v v cc undervoltage lockout v cc_uvlo v cc falling 6.6 v output driver peak source current v cc = 11v (externally forced) 570 ma peak sink current v cc = 11v (externally forced) 1000 ma ndrv high-side driver resistance r oh v cc = 11v, externally forced, ndrv sourcing 50ma 412 ? ndrv low-side driver resistance r ol v cc = 11v, externally forced, ndrv sinking 50ma 1.6 4 ? pwm comparator opto input bias current v opto = v ss_ shdn -1.00 +1.00 a opto control range 23v slope compensation v scomp max5941a 26 mv/s thermal shutdown thermal shutdown temperature 150 c thermal hysteresis 25 c current limit cs threshold voltage v ilim v opto = 4v 419 465 510 mv cs input bias current 0v v cs 2v, v opto = 4v -1 +1 a current-limit comparator propagation delay 25mv overdrive on cs, v opto = 4v 180 ns cs blanking time v opto = 4v 70 ns oscillator clock frequency range v opto = 4v 235 275 314 khz max5941a, v opto = 4v 75 85 max duty cycle max5941b, v opto = 4v 44 50 % soft-start ss source current i sso v ss (shdn ) = 0v 2.0 4.6 6.5 a ss sink current 1ma peak soft-start voltage clamp no external load 2.331 2.420 2.500 v v ss_ shdn falling (note 11) 0.25 0.37 0.41 shutdown threshold v ss_ shdn rising (note 11) 0.53 0.59 0.65 v
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices _______________________________________________________________________________________ 5 i in i ini +1 i ini i offset dr i 1v v ini v ini +1 i offset ? i ini - v ini dr i dr i ? (v ini + 1 - v ini ) = 1v (i ini + 1 - i ini ) (i ini + 1 - i ini ) figure 1. effective differential input resistance/offset current note 1: all min/max limits for the pd interface are production tested at +85 c (extended grade)/+70 c (commercial grade). limits at +25 c and -40 c are guaranteed by design. all pwm controller min/max limits are 100% production tested at +25 c and +85 c (extended grade)/+70 c (commercial grade). limits at -40 c are guaranteed by design, unless otherwise noted. note 2: the input offset current is illustrated in figure 1. note 3: effective differential input resistance is defined as the differential resistance between gnd and v ee without any external resistance. note 4: classification current is turned off whenever the ic is in power mode. note 5: see table 2 in the pd classification mode section. r disc and r cl must be 100ppm or better. note 6: see thermal dissipation section for details. note 7: when uvlo is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k ? ( 1%), the turn- on threshold set point for the power mode is defined by the external resistor-divider. make sure the voltage on the uvlo pin does not exceed its maximum rating of 8v when v in is at the maximum voltage. note 8: when the v uvlo is below v th, g, uvlo, the max5941 sets the turn-on voltage threshold internally (v uvlo,on ). note 9: an input voltage or v uvlo glitch below their respective thresholds shorter than or equal to t off_dly does not cause the max5941a/max5941b to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12v). note 10: pgood references to out while pgood references to v ee . note 11: guaranteed by design.
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 6 _______________________________________________________________________________________ detection current vs. input voltage max5941a/b toc01 input voltage (v) detection current (ma) 8 6 4 2 0.10 0.20 0.30 0.40 0.05 0.15 0.25 0.35 0.45 0 010 r disc = 25.5k ? gnd = v+ = v- = out classification current vs. input voltage max5941a/b toc02 input voltage (v) classification current (ma) 25 20 15 5 15 25 35 10 20 30 40 0 10 30 class 0 class 1 class 2 class 3 class 4 effective differential input resistance vs. input voltage max5941a/b toc03 input voltage (v) effective differential input resistance (m ? ) 15 10 5 0.5 1.5 2.5 1.0 2.0 3.0 3.5 0 0 offset current vs. input voltage max5941a/b toc04 input voltage (v) offset current ( a) 8 6 4 2910 7 5 3 -2.0 -1.0 -3.0 -2.5 -1.5 -0.5 0 -3.5 111 normalized uvlo vs. temperature max5941a/b toc05 temperature ( c) normalized uvlo 60 35 10 -15 0.996 1.004 0.992 0.994 1.000 1.008 1.002 0.998 1.006 1.010 0.990 -40 85 uvlo = v ee pgood output low voltage vs. current max5941a/b toc06 i sink (ma) v pgood (mv) 16 12 48 40 20 80 120 160 60 100 140 180 200 0 020 pgood output low voltage vs. current max5941a/b toc07 i sink (ma) v pgood (mv) 16 12 8 4 50 100 200 300 150 250 350 400 0 020 out leakage current vs. temperature max5941a/b toc08 input voltage (v) out leakage current (na) 60 35 10 -15 4 8 12 16 20 0 -40 85 v out = 67v inrush current control (v in = 12v) max5941toc09 v gate 5v/div i inrush 100ma/div v out 10v/div p good 10v/div 1ms/div typical operating characteristics (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = out = open, uvlo = v ee , v dd = 13v, ndrv floating, t a = t min to t max . typical values are at t a = +25 c. all voltages are referenced to v ee (for graphs 1 11 in the typical operating characteristics ), all voltages are referenced to v- (for graphs 12 30 in the typical operating characteristics ), unless otherwise noted.)
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices _______________________________________________________________________________________ 7 inrush current control (v in = 48v) max5941toc10 v gate 5v/div i inrush 100ma/div v out 50v/div p good 50v/div 2ms/div inrush current control (v in = 67v) max5941toc11 v gate 5v/div i inrush 100ma/div v out 50v/div p good 50v/div 2ms/div 0.999 1.000 1.001 1.002 1.003 -40 0 -20 20 40 60 80 v ss_shdn vs. temperature (at the end of soft-start) max5941a/b toc12 temperature ( c) opto = cs = v- v ss_shdn (v) (normalized to v ref = 2.4v) 273 274 276 275 277 278 -40 0 -20 20 40 60 80 ndrv frequency vs. temperature max5941a/b toc13 temperature ( c) ndrv frequency (khz) v opto = 4v, cs = v- 80.4 80.6 80.5 80.8 80.7 80.9 81.0 -40 20 40 -20 0 60 80 maximum duty cycle vs. temperature max5941a/b toc14 temperature ( c) maximum duty cycle (%) v opto = 4v, cs = v- 46.8 47.2 47.0 47.6 47.4 47.8 48.0 -40 20 40 -20 0 60 80 maximum duty cycle vs. temperature max5941a/b toc15 temperature ( c) max duty cycle (%) v opto = 4v, cs = v- v+ supply current vs. temperature max5941a/b toc16 1.38 1.39 1.41 1.40 1.44 1.45 1.43 1.42 1.46 v+ input current (ma) -40 0 20 -20 40 60 80 temperature ( c) v opto = 4v, v dd = cs = v- typical operating characteristics (continued) (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = out = open, uvlo = v ee , v dd = 13v, ndrv floating, t a = t min to t max . typical values are at t a = +25 c. all voltages are referenced to v ee (for graphs 1 11 in the typical operating characteristics ), all voltages are referenced to v- (for graphs 12 30 in the typical operating characteristics ), unless otherwise noted.)
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 8 _______________________________________________________________________________________ 185 188 187 186 190 189 194 193 192 191 195 -40 -20 0 20 40 60 80 v+ shutdown current vs. temperature max5941a/b toc19 temperature ( c) v+ shutdown current ( a) v+ = 67v, opto = ss_shdn = cs = v-, v dd = 13v 0.483 0.484 0.486 0.485 0.487 0.488 -40 0 -20 20 40 60 80 cs threshold voltage vs. temperature max5941a/b toc20 temperature ( c) cs threshold voltage (v) v opto = 4v, v+ = 67v ndrv resistance vs. temperature max5941a/b toc21 1.0 1.5 2.5 2.0 4.0 4.5 3.5 3.0 5.0 ndrv resistance ( ? ) -40 0 20 -20 40 60 80 temperature ( c) high-side driver low-side driver 170 176 174 172 180 178 188 186 184 182 190 -40 -20 0 20 40 60 80 current-limit delay vs. temperature max5941a/b toc22 temperature ( c) current-limit delay (ns) v opto = 4v, 100mv overdrive on cs 2.400 2.402 2.406 2.404 2.408 2.410 01015 5 2025303540 v ss_shdn vs. v dd max5941a/b toc23 v dd (v) v ss_shdn ( v ) 267.0 268.0 267.5 269.0 268.5 269.5 270.0 270.5 271.0 01015 5 2025303540 ndrv frequency vs. v dd max5941a/b toc24 v dd (v) ndrv frequency (khz) v opto = 4v, cs = v- typical operating characteristics (continued) (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = out = open, uvlo = v ee , v dd = 13v, ndrv floating, t a = t min to t max . typical values are at t a = +25 c. all voltages are referenced to v ee (for graphs 1 11 in the typical operating characteristics ), all voltages are referenced to v- (for graphs 12 30 in the typical operating characteristics ), unless otherwise noted.) 4.50 4.65 4.60 4.55 4.75 4.70 4.95 4.90 4.85 4.80 5.00 -40 -20 0 20 40 60 80 soft-start source current vs. temperature max5941a/b toc17 temperature ( c) soft-start source current ( a) v+ = 67v, opto = v cc cs = ss_shdn = v- 11.00 11.05 11.15 11.10 11.20 11.25 -40 0 -20 20 40 60 80 v+ input current vs. temperature (after startup) max5941a/b toc18 temperature ( c) v+ input current ( a) v+ = 67v, v opto = 4v, cs = v-, v dd = 13v
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices _______________________________________________________________________________________ 9 47.0 47.2 47.1 47.4 47.3 47.6 47.5 47.7 47.9 47.8 48.0 01015 5 2025303540 maximum duty cycle vs. v dd max5941a/b toc25 v dd (v) maximum duty cycle (%) v opto = 4v, cs = v- driver powered from v+ driver powered from v dd 9.5 9.6 9.8 9.7 10.0 10.1 9.9 10.2 01015 5 2025303540 v cc vs. v dd max5941a/b toc26 v dd (v) v cc (v) device powered from v dd device powered from v+ 1.31 1.33 1.32 1.36 1.35 1.34 1.39 1.38 1.37 1.40 040 20 60 80 100 v+ supply current vs. v+ voltage max5941a/b toc27 v+ voltage (v) v+ supply current (ma) v opto = 4v, cs = v dd = v- 0 6 4 2 8 10 12 040 30 10 20 50 60 70 80 90 110 v+ input current vs. voltage (after startup) max5941a/b toc28 v+ voltage (v) v+ input current ( a) 100 v opto = 4v, cs = v-, v dd = 13v 9.0 9.4 9.2 9.8 9.6 10.2 10.0 10.4 v cc voltage vs. v cc current max5941a/b toc29 v cc current (ma) v cc voltage (v) 0 5 10 15 20 v+ = 67v, opto = cs = v- v dd = 36v v dd = 13v 9.0 9.3 9.2 9.1 9.4 9.5 9.6 9.7 9.8 9.9 10.0 0 5 10 15 20 v cc voltage vs. v cc current max5941a/b toc30 v cc current (ma) v cc voltage (v) v dd = opto = cs = v- v+ = 48v v+ = 67v v+ = 36v v+ = 24v typical operating characteristics (continued) (v in = (gnd - v ee ) = 48v, gate = pgood = pgood = out = open, uvlo = v ee , v dd = 13v, ndrv floating, t a = t min to t max . typical values are at t a = +25 c. all voltages are referenced to v ee (for graphs 1 11 in the typical operating characteristics ), all voltages are referenced to v- (for graphs 12 30 in the typical operating characteristics ), unless otherwise noted.)
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 10 ______________________________________________________________________________________ max5941a/max5941b pin description pin name function 1v+ h i g h- v ol tag e s tar tup inp ut. refer enced to v - . c onnect d i r ectl y to an i np ut vol tag e r ang e b etw een 18v to 67v . c onnects i nter nal l y to a hi g h- vol tag e l i near r eg ul ator that g ener ates v c c d ur i ng star tup . ti e v + to gn d . 2v dd line regulator input. referenced to v-. v dd is the input to the linear regulator that generates v cc . for supply voltages less than 36v, connect v dd and v+ to the supply. for supply voltages greater than 36v, v dd receives its power from the tertiary winding of the transformer and accepts voltages from 13v to 36v. bypass v dd to v- with a 4.7f capacitor. 3 opto optocoupler input. referenced to v-. the control voltage range on this input is 2v to 3v. 4 ss_ shdn soft-start timing capacitor connection. referenced to v-. ramp time to full current limit is approximately 0.45ms/nf. bypass with a minimum 10nf capacitor to v-. a 2.4v reference voltage appears across the capacitor. disable the pwm controller by pulling ss_ shdn below 0.25v. tie to pgood to enable pwm controller automatically from the pd interface. 5 uvlo undervoltage lockout programming input for power mode. referenced to v ee . when uvlo is above its threshold, the device enters the power mode. connect uvlo to v ee to use the default undervoltage lockout threshold. connect uvlo to an external resistor-divider to define a threshold externally. the series resistance value of the external resistors must add to 25.5k ? (1%) and replaces the detection resistor. to keep the device in undervoltage lockout, pull uvlo between v th,g,uvlo and v ref,uvlo . 6 rcl c l assi fi cati on s etti ng . refer enced to v e e . ad d a r esi stor fr om rc l to v e e to set a p d cl ass ( see tab l es 1 and 2) . 7 gate gate of internal n-channel power mosfet. referenced to v ee . gate sources 10a when the device enters the power mode. connect an external 100v ceramic capacitor from gate to v out to program the inrush current. pull gate to v ee to turn off the internal mosfet. the detection and classification functions operate normally when gate is pulled to v ee . 8v ee negative input power. source of the integrated isolation n-channel power mosfet. connect v ee to -48v. 9 out output voltage. referenced to v ee . drain of the integrated isolation n-channel power mosfet. connect out to v-. 10 pgood power-good indicator output, active high, open drain. pgood is referenced to out. pgood goes high impedance when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood is pulled to out (given that v out is at least 5v below gnd). connect pgood directly (no external pullup required) to ss_ shdn to enable/disable the pwm controller. 11 pgood power-good indicator output, active low, open drain. pgood is referenced to v ee . pgood is pulled to v ee when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood goes high impedance. 12 gnd ground. referenced to v ee . gnd is the positive input power. connect to v+. 13 cs current-sense input. referenced to v-. turns power switch off if v cs rises above 465mv for cycle-by-cycle current limiting. cs is also the feedback for the current-mode controller. cs connects to the pwm controller through a leading-edge blanking circuit. 14 v- v- is the ground terminal of the pwm controller. connect to gnd. 15 ndrv gate drive. referenced to v-. drives a high-voltage external n-channel power mosfet. 16 v cc regulated ic supply. referenced to v-. provides power for max5941_. v cc is regulated from v dd during normal operation and from v+ during startup. bypass v cc with a 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor to v-.
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices ______________________________________________________________________________________ 11 max5941a/max5941b class usage r cl ( ? ) maximum power used by pd (w) 0 default 10k 0.44 to 12.95 1 optional 732 0.44 to 3.84 2 optional 392 3.84 to 6.49 3 optional 255 6.49 to 12.95 4 not allowed 178 reserved* *class 4 reserved for future use. table 1. pd power classification/r cl selection detailed description the max5941a/max5941b integrate a complete power ic for powered devices (pds) in a power-over-ethernet (poe) system. the max5941a/max5941b provide pd interface and a compact dc-dc pwm controller suitable for flyback and forward converters in either isolated or nonisolated designs. the max5941a/max5941b powered device (pd) inter- face complies with the ieee 802.3af standard, providing the pd with a detection signature, a classification signa- ture, and an integrated isolation switch with programma- ble inrush current control. these devices also feature power-mode undervoltage lockout (uvlo) with wide hys- teresis, and power-good status outputs. an integrated mosfet provides pd isolation during detection and classification. the max5941a/max5941b guarantee a leakage current offset of less than 10a dur- ing the detection phase. a programmable current limit prevents high inrush current during power-on. the devices feature power-mode uvlo with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to ensure glitch-free transition between detection, classification, and power-on/off phas- es. the max5941a/max5941b provide both active-high (pgood) and active-low ( pgood ) outputs. both devices offer an adjustable uvlo threshold with a default value compliant to the ieee 802.3af standard. the max5941a/max5941b are designed to work with or without an external diode bridge in front of the pd. use the max5941a/max5941b pwm current-mode con- trollers to design flyback- or forward-mode power sup- plies. current-mode operation simplifies control-loop design while enhancing loop stability. an internal high- voltage startup regulator allows the device to connect directly to the input supply without an external startup resistor. current from the internal regulator starts the con- troller. once the tertiary winding voltage is established, the internal regulator is switched off and bias current for running the pwm controller is derived from the tertiary winding. the internal oscillator is set to 275khz and trimmed to 10%. this permits the use of small magnetic components to minimize board space. both the max5941a and max5941b can be used in power sup- plies providing multiple output voltages. a functional dia- gram of the pwm controller is shown in figure 4. typical applications circuits for forward and flyback topologies are shown in figure 5 and figure 6, respectively. powered device interface operating modes the powered device (pd) front-end section of the max5941a/max5941b operates in three different modes: pd detection signature, pd classification, and pd power, depending on its input voltage (v in = gnd - v ee ). all voltage thresholds are designed to operate with or with- out the optional diode bridge while still complying with the ieee 802.3af standard (see application circuit 1). detection mode (1.4v v in 10.1v) in detection mode, the power source equipment (pse) applies two voltages on v in in the range of 1.4v to 10.1v (1v step minimum), and then records the current measurements at the two points. the pse then com- putes ? v/ ? i to ensure the presence of the 25.5k ? sig- nature resistor. in this mode, most of the max5941a/ max5941b internal circuitry is off and the offset current is less than 10a. if the voltage applied to the pd is reversed, install pro- tection diodes on the input terminal to prevent internal damage to the max5941a/max5941b (see figure 7). since the pse uses a slope technique ( ? v/ ? i) to calcu- late the signature resistance, the dc offset due to the protection diodes is subtracted and does not affect the detection process. classification mode (12.6v v in 20v) in the classification mode, the pse classifies the pd based on the power consumption required by the pd. this allows the pse to efficiently manage power distribu- tion. the ieee 802.3af standard defines five different classes as shown in table 1. an external resistor (r cl ) connected from rcl to v ee sets the classification current.
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 12 ______________________________________________________________________________________ max5941a/max5941b r1 21.8v 39v gnd uvlo gnd uvlo gate r2 r3 max5941b classification rcl pgood 6.8v en ref 2.4v, 0.8 hyst 2.4v, ref 200mv v ee v gate , 6v 1.2v, ref 5v, ref q4 pgood out q3 q1 q2 en figure 2. powered device interface block diagram class current seen at v in (ma) ieee 802.3af pd classification current specification (ma) class r cl ( ? )v in * (v) min max min max 0 10k 12.6 to 20 0 4 0 4 1 732 12.6 to 20 9 12 9 12 2 392 12.6 to 20 17 20 17 20 3 255 12.6 to 20 26 30 26 30 4 178 12.6 to 20 36 42 36 44 *v in is measured across the max5941 input pins (v ee and gnd), which does not include the diode bridge voltage drop. table 2. setting classification current
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices ______________________________________________________________________________________ 13 max5941a/max5941b the pse determines the class of a pd by applying a volt- age at the pd input and measures the current sourced out of the pse. when the pse applies a voltage between 12.6v and 20v, the max5941a/max5941b exhibit a cur- rent characteristic with values indicated in table 2. the pse uses the classification current information to classify the power requirement of the pd. the classification cur- rent includes the current drawn by the 25.5k ? detection signature resistor and the supply current of the max5941a/max5941b so that the total current drawn by the pd is within the ieee 802.3af standard figures. the classification current is turned off whenever the device is in power mode. power mode during power mode, when v in rises above the undervoltage lockout threshold (v uvlo,on ), the max5941a/ max5941b gradually turn on the internal n- channel mosfet q1 (see figure 2). the max5941a/ max5941b charge the gate of q1 with a constant current source (10a, typ). the drain-to-gate capacitance of q1 limits the voltage rise rate at the drain of mosfet, there- by limiting the inrush current. to reduce the inrush cur- rent, add external drain-to-gate capacitance (see the inrush current section). when the drain of q1 is within 1.2v of its source voltage and its gate-to-source voltage is above 5v, the max5941a/max5941b assert the pgood/ pgood outputs. the max5941a/max5941b have a wide uvlo hysteresis and turn-off deglitch time to compensate for the high impedance of the twisted-pair cable. undervoltage lockout the max5941a/max5941b operate up to a 67v supply voltage with a default uvlo turn-on set at 39v and a uvlo turn-off set at 30v. adjust the uvlo threshold using a resistor-divider connected to uvlo (see figure 3). when the input voltage is above the uvlo threshold (v uvlo,on ), the ic is in power mode and the mosfet is on. when the input voltage goes below the uvlo thresh- old (v uvlo,off ) for more than t off_dly , the mosfet turns off. to adjust the uvlo threshold, connect an external resistor-divider from gnd to uvlo and from uvlo to v ee . use the following equations to calculate r1 and r2 for a desired uvlo threshold: r1 = 25.5k ? - r2 where v in, ex is the desired uvlo threshold. since the resistor-divider replaces the 25.5k ? pd detection resis- tor, ensure that the sum of r1 and r2 equals 25.5k ? 1%. when using the external resistor-divider, the max5941 has an external reference voltage hysteresis of 20% (typ). in other words, when uvlo is programmed externally, the turn-off threshold is 80% (typ) of the new uvlo turn-on threshold. inrush current limit the max5941a/max5941b charge the gate of the inter- nal mosfet with a constant current source (10a, typ). the drain-to-gate capacitance of the mosfet limits the voltage rise rate at the drain, thereby limiting the inrush current. add an external capacitor from gate to out to further reduce the inrush current. use the following equation to calculate the inrush current: the recommended inrush current for a poe application is 100ma. pgood/ pgood outputs pgood is an open-drain, active-high logic output. pgood goes high impedance when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood is pulled to v out (given that v out is at least 5v below gnd). connect pgood to ss_ shdn to enable the pwm controller. no external pullup resistor is required. pgood is an open-drain, active-low logic output. pgood is pulled to v ee when v out is within 1.2v of v ee and when gate is 5v above v ee . otherwise, pgood goes high impedance. iix c c inrush g out gate = rkx v v ref uvlo in ex 2255 = . , , ? r1 uvlo gnd v ee r2 v in = 24v to 60v max5941a max5941b figure 3. setting undervoltage lockout with an external resistor-divider
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 14 ______________________________________________________________________________________ thermal dissipation during classification mode, if the pse applies the maxi- mum dc voltage, the maximum voltage drop from gnd to v rcl will be 13v. if the maximum classification current of 42ma flows through the max5941a/max5941b, then the maximum dc power dissipation will be close to 546mw, which is slightly higher than the maximum dc power dissipation of the ic at maximum operating tem- perature. however, according to the ieee 802.3af stan- dard, the duration of the classification mode is limited to 75ms (max). the max5941a/max5941b handles the maximum classification power dissipation for the maxi- mum duration time without sustaining any internal dam- age. if the pse violates the ieee 802.3af standard by exceeding the 75ms maximum classification duration, it may cause internal damage to the ic. pwm controller current-mode control the max5941a/max5941b offer current-mode control operation with added features such as leading-edge blanking with dual internal path that only blanks the sensed current signal applied to the input of the pwm comparator. the current-limit comparator monitors the cs pin at all times and provides cycle-by-cycle current limit without being blanked. the leading-edge blanking of the cs signal prevents the pwm comparator from prematurely terminating the on cycle. the cs signal contains a leading-edge spike that is the result of the mosfet gate charge current, capacitive and diode reverse recovery current of the power circuit. since this leading-edge spike is normally lower than the current limit comparator threshold, current limiting is not blanked and cycle-by-cycle current limiting is provided under all conditions. use the max5941a in discontinuous flyback applica- tions where wide line voltage and load current variation is expected. use the max5941b for single transistor forward converters where the maximum duty cycle must be limited to less than 50%. under certain conditions, it may be advantageous to use a forward converter with greater than 50% duty cycle. for those cases, use the max5941a. the large duty cycle results in much lower operating primary rms currents through the mosfet switch and in most cases a smaller output filter inductor. the major disadvantage to this is that the mosfet voltage rating must be higher and that slope compensation must be provided to sta- bilize the inner current loop. the max5941a provides internal slope compensation. optocoupled feedback isolated voltage feedback is achieved by using an opto- coupler and a shunt regulator as shown in figure 5. the output voltage set-point accuracy is a function of the accuracy of the shunt regulator and feedback resistor- divider tolerance. internal regulators the internal regulators of the max5941a/max5941b enable initial startup without a lossy startup resistor and regulate the voltage at the output of a tertiary (bias) wind- ing to provide power for the ic. at startup, v+ is regulat- ed down to v cc to provide bias for the device. the v dd regulator then regulates from the output of the tertiary winding to v cc . this architecture allows the tertiary wind- ing to have only a small filter capacitor at its output thus eliminating the additional cost of a filter inductor. when designing the tertiary winding, calculate the num- ber of turns so the minimum reflected voltage is always higher than 12.7v. the maximum reflected voltage must be less than 36v. to reduce power dissipation, the high-voltage regulator is disabled when the v dd voltage reaches 12.7v. this greatly reduces power dissipation and improves effi- ciency. if v cc falls below the undervoltage lockout threshold (v cc = 6.6v), the low-voltage regulator is dis- abled, and soft-start is reinitiated. in undervoltage lock- out the mosfet driver output (ndrv) is held low. if the input voltage range is between 13v and 36v, v+ and v dd may be connected to the line voltage provided that the maximum power dissipation is not exceeded. this eliminates the need for a tertiary winding. pwm controller undervoltage lockout, soft-start, and shutdown the soft-start feature of the max5941a/max5941b allows the load voltage to ramp up in a controlled man- ner, thus eliminating output voltage overshoot. while the controller is in undervoltage lockout, the capacitor connected to the ss_ shdn pin is dis- charged. upon coming out of undervoltage lockout, an internal current source starts charging the capacitor to initiate the soft-start cycle. use the following equation to calculate total soft-start time: where c ss is the soft-start capacitor as shown in figure 5. operation begins when v ss_ shdn ramps above 0.6v. when soft-start has completed, v ss_ shdn is regulated t ms c startup ss = 045 . nf
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices ______________________________________________________________________________________ 15 high- voltage regulator in en out bias winding regulator in en out slope compensation 26mv/ s 275khz oscillator 70ns blanking r s q 80%/50% duty cycle clamp ilim buf uvlo v- v+ v dd opto ss_shdn pwm v dd - ok v cc ndrv cs vb 4 a 3r r 5k ? 2.4v 6.6v 0.7v 125mv 0.4v 26mv/ s max5941a only figure 4. max5941a/max5941b pwm controller functional diagram
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 16 ______________________________________________________________________________________ to 2.4v, the internal voltage reference. pull v ss_ shdn below 0.25v to disable the controller. undervoltage lockout shuts down the controller when v cc is less than 6.6v. the regulators for v+ and the ref- erence remain on during shutdown. current-sense comparator the current-sense (cs) comparator and its associated logic limit the peak current through the mosfet. current is sensed at cs as a voltage across a sense resistor between the source of the mosfet and gnd. to reduce switching noise, connect cs to the external mosfet source through a 100 ? resistor or an rc low- pass filter (figures 5, 6). select the current-sense resis- tor, r sense , according to the following equation: where i limprimary is the maximum peak primary-side current. when v cs > 465mv, the power mosfet switches off. the propagation delay from the time the switch current reaches the trip level to the driver turn-off time is 170ns. ri sense limprimary = 0 465 ./ v max5941b v dd uvlo rcl v+ gnd ss_shdn pgood pgood gate v ee ndrv cs v- v cc opto v in (30v to 72v) v out optocoupler c dd 47 f c ss 0.1 f r disc 25.5k ? 3k ? 4.75k ? c cc 10 f 100 ? r sense 100m ? 20 ? r 1 25.5k ? r 2 8.25k ? c out 3 560 f 0.1 f c in 3 0.47 f l1 4.7 h 0.1 f 240k ? n t n r n p n s m1 irf640n 4.7nf 250vac tlv431 1n4148 6 cmhd2003 14 5 1nf sbl204oct 5v/10a 220 ? 14 r cl out figure 5. forward converter
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices ______________________________________________________________________________________ 17 pwm comparator and slope compensation an internal 275khz oscillator determines the switching frequency of the controller. at the beginning of each cycle, ndrv switches the n-channel mosfet on. ndrv switches the external mosfet off after the maxi- mum duty cycle has been reached, regardless of the feedback. the max5941b uses an internal ramp generator for slope compensation. the internal ramp signal is reset at the beginning of each cycle and slews at 26mv/s. the pwm comparator uses the instantaneous current, the error voltage, the internal reference, and the slope compensation (max5941a only) to determine when to switch the n-channel mosfet off. in normal operation, the n-channel mosfet turns off when: where i primary is the current through the n-channel mosfet, v ref is the 2.4v internal reference, and v scomp is a ramp function starting at zero and slewing at 26mv/s (max5941a only). when using the max5941a in a forward-converter configuration, the fol- lowing condition must be met to avoid control-loop sub- harmonic oscillations: irv-v-v primary sense opto ref scomp > max5941a v dd v+ gnd ndrv cs v- out v cc opto v in v out optocoupler c dd c cc 100 ? r sense r 1 r 2 c out c in n t n p n s m1 4.7nf 250vac tlv431 220 ? uvlo rcl gate ss_shdn pgood pgood v ee c ss r disc 25.5k ? r cl figure 6. flyback converter
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 18 ______________________________________________________________________________________ where k = 0.75 to 1, and n s and n p are the number of turns on the secondary and primary side of the trans- former, respectively. l is the output filter inductor. this makes the output inductor current downslope as refer- enced across r sense equal to the slope compensa- tion. the controller responds to transients within one cycle when this condition is met. n-channel mosfet gate driver ndrv drives an n-channel mosfet. ndrv sources and sinks large transient currents to charge and dis- charge the mosfet gate. to support such switching transients, bypass v cc with a ceramic capacitor. the average current as a result of switching the mosfet is the product of the total gate charge and the operating frequency. it is this current plus the dc quiescent cur- rent that determines the total operating current. applications information design example the following is a general procedure for designing a forward converter (figure 5) using the max5941b: 1) determine the requirements. 2) set the output voltage. 3) calculate the transformer primary to secondary winding turns ratio. 4) calculate the reset to primary winding turns ratio. 5) calculate the tertiary to primary winding turns ratio. 6) calculate the current-sense resistor value. 7) calculate the output inductor value. 8) select the output capacitor. the circuit in figure 5 was designed as follows: 1) 30v v in 67v, v out = 5v, i out = 10a, v ripple 50mv. turn-on threshold is set at 38.6v. 2) to set the output voltage, calculate the values of resistors r1 and r2 according to the following equation: where v ref is the reference voltage of the shunt regulator, and r 1 and r 2 are the resistors shown in figures 5 and 6. 3) the turns ratio of the transformer is calculated based on the minimum input voltage and the lower limit of the maximum duty cycle for the max5941b (44%). to enable the use of mosfets with drain-source breakdown voltages of less than 200v, use the max5941b with the 50% maximum duty cycle. calculate the turns ratio according to the following equation: where: n s /n p = turns ratio (n s is the number of secondary turns and n p is the number of primary turns). v out = output voltage (5v). v d1 = voltage drop across d1 (typically 0.5v for power schottky diodes). d max = minimum value of maximum operating duty cycle (44%). v in_min = minimum input voltage (30v). in this example: choose n p based on core losses and dc resis- tance. use the turns ratio to calculate n s , rounding up to the nearest integer. in this example, n p = 14 and n s = 6. for a forward converter, choose a transformer with a magnetizing inductance in the neighborhood of 200h. energy stored in the magnetizing inductance of a forward converter is not delivered to the load and must be returned back to the input; this is accomplished with the reset winding. the transformer primary to secondary leakage inductance should be less than 1h. note that all leakage energy will be dissipated across the mos- fet. snubber circuits may be used to direct some or all of the leakage energy to be dissipated across a resistor. to calculate the minimum duty cycle (d min ), use the following equation: = where v in_max is the maximum input voltage (67v). d v v n n -v min out in_max s p d1 = = 17 7 . n n 5v + 0.5v 0.44 s p () = 044 30 0 395 . . v n n vvd dv s p out d1 max max in_min + () v v r rr ref out 2 12 = + n n kr v s p sense out = l mv s 26 /
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices ______________________________________________________________________________________ 19 4) the reset winding turns ratio (n r /n p ) needs to be low enough to guarantee that the entire energy in the transformer is returned to v+ within the off cycle at the maximum duty cycle. use the following equa- tion to determine the reset winding turns ratio: where: n r /n p = reset winding turns ratio. d max = maximum value of maximum duty cycle: round n r to the nearest smallest integer. the turns ratio of the reset winding (n r /n p ) deter- mines the peak voltage across the n-channel mos- fet. use the following equation to determine the maxi- mum drain-source voltage across the n-channel mosfet: v dsmax = maximum mosfet drain-source voltage. v in_max = maximum input voltage: choose mosfets with appropriate avalanche power ratings to absorb any leakage energy. 5) choose the tertiary winding turns ratio (n t /n p ) so that the minimum input voltage provides the minimum operating voltage at v dd (13v). use the following equation to calculate the tertiary winding turns ratio: where: v ddmin is the minimum v dd supply voltage (13v). v ddmax is the maximum v dd supply voltage (30v). v in_min is the minimum input voltage (30v). v in_max is the maximum input voltage (67v in this design example). n p is the number of turns of the primary winding. n t is the number of turns of the tertiary winding: choose n t = 7. 6) choose r sense according to the following equation: where: v ilim is the current-sense comparator trip threshold voltage (0.465v). n s /n p is the secondary side turns ratio (5/14 in this example). i outmax is the maximum dc output current (10a in this example): 7) choose the inductor value so that the peak ripple current (lir) in the inductor is between 10% and 20% of the maximum output current: where v d is the output schottky diode forward volt- age drop (0.5v) and lir is the ratio of inductor rip- ple current to dc output current: 8) the size and esr of the output filter capacitor deter- mine the output ripple. choose a capacitor with a low esr to yield the required ripple voltage. use the following equations to calculate the peak-to- peak output ripple: vv v ripple ripple esr ripple c =+ ,, 22 l - () () = 5 5 1 0 198 0 4 275 10 401 .. . . khz a h l v- out + () () vd lir khz i d min outmax 1 2 275 r sense =? 0 465 6 14 12 10 90 4 . . . v m r v n n sense ilim s p 12 .i outmax 13 7 4 36 7 14 639 767 .. .. 30 1n 67 n t t ? v v nn v v n ddmin in_min pt ddmax in_max p + ? + 07 07 . . v1 + 14 14 dsmax ? ? ? ? ? ? ? = 67 134 vv vv 1 + n n dsmax in_max p r ? ? ? ? ? ? ? n1 1- 0.5 0.5 r ? = 414 nn 1-d d rp max max ?
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 20 ______________________________________________________________________________________ component suppliers website international rectifier www.irf.com fairchild www.fairchildsemi.com power fets vishay-siliconix www.vishay.com/brands/siliconix/main.html dale-vishay www.vishay.com/brands/dale/main.html current-sense resistors irc www.irctt.com/pages/index.cfm on semi www.onsemi.com general semiconductor www.gensemi.com diodes central semiconductor www.centralsemi.com sanyo www.sanyo.com taiyo yuden www.t-yuden.com capacitors avx www.avxcorp.com coiltronics www.cooperet.com coilcraft www.coilcraft.com magnetics pulse engineering www.pulseeng.com table 3. component suppliers where: v ripple is the combined rms output ripple due to v ripple,esr , the esr ripple, and v ripple,c , the capacitive ripple. calculate the esr ripple and capacitive ripple as follows: v ripple,esr = i ripple x esr v ripple,c = i ripple /(2 x x 275khz x c out ) layout recommendations all connections carrying pulsed currents must be very short, be as wide as possible, and have a ground plane as a return path. the inductance of these connections must be kept to a minimum due to the high di/dt of the currents in high-frequency switching power converters. current loops must be analyzed in any layout pro- posed, and the internal area kept to a minimum to reduce radiated emi. ground planes must be kept as intact as possible.
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices ______________________________________________________________________________________ 21 phy gnd -48v vreg tx rx rj-45 df025a df025a power over spare pairs 3 6 1 2 4 5 7 8 * r1 and r2 are optional and when used, they must total to 25.5k ? and replace the 25.5k ? resistor. * optional. power-over signal pairs + - + - ndrv gnd v+ v dd v cc 68nf 60v gnd smbj58ca -48v r disc = 25.5k ? rcl rcl uvlo gate v ee *c gate *d2 *d1 **r1 **r2 cs v- ss_shdn pgood pgood opto optocoupler tl431 out v cc vreg max5941_ figure 7. pd with power-over-ethernet (power is provided by either the signal pairs or the spare pairs)
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices 22 ______________________________________________________________________________________ * r1 and r2 are optional and when used, they must total to 25.5k ? and replace the 25.5k ? resistor. * optional. ndrv v+ v+ v dd cs gnd ss_shdn v cc optocoupler tl431 opto vreg2 max5014 power-supply circuit 1 power-supply circuit 2 ndrv gnd v+ v dd 68nf 60v gnd -48v r disc = 25.5k ? rcl rcl uvlo gate v ee *c gate *d2 *d1 **r1 **r2 cs v- ss_shdn pgood v cc opto optocoupler tl431 out vreg1 max5941_ pgood figure 8. power-supply circuit 1 enabling pwm controller of a second power circuit
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices ______________________________________________________________________________________ 23 chip information transistor count: 4232 process: bicmos typical operating circuit ndrv gnd v+ v dd v cc 60v gnd -48v rcl uvlo gate v ee c gate cs v- ss_shdn pgood pgood opto optocoupler tl431 out v cc vreg max5941a max5941b r disc = 25.5k ?
max5941a/max5941b ieee 802.3af-compliant power-over-ethernet interface/pwm controller for power devices maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 28l 16l soic.eps

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